1. Field of the Invention
The present invention generally relates to read only memories (ROM) having the respective states of the cells are set on manufacturing of the integrated circuit containing the memory. The present invention more specifically relates to the forming of an array of memory cells formed of MOS transistors. It applies whether the programming of each cell is performed by the taking of a contact on one of the source or drain regions of the transistor (memory generally known as a “ROM contact”), or it is performed by the forming of a conductive via from a source or drain contact area to a metal track conveying the signals (memory generally known as a “ROM via”).
2. Description of the Related Art
FIG. 1 very schematically shows in the form of blocks an example of a ROM of the type to which the present invention applies. Such a structure is intended to be made in integrated form, possibly with other components.
A ROM mainly comprises an array 1 of memory cells having word lines WL (for example, in rows) and bit lines BL (for example, in columns) respectively connected to row (ROWDEC) and column (COLDEC) decoding circuits 2 and 3, circuit 3 also comprising sense amplifiers (SA). Circuits 2 and 3 communicate with an input/output circuit 4 (ADD/DEC/I/O) also comprising an address decoder. Circuit 4 is connected to an address, data, and control bus 5, communicating with the outside of the memory.
FIGS. 2A and 2B partially and schematically show a conventional example of the architecture of an array 1 of ROM-type memory cells. FIG. 2A shows the equivalent electric diagram of the MOS transistors while FIG. 2B is a simplified top view of the active areas and of the overlying polysilicon and contact recovery metallization lines.
In the example of FIGS. 2A and 2B, eight memory cells distributed over two bit lines BLi and BLi+1 and four word lines WLj, WLj+1, WLj+2, and WLj+3 have been shown. Each cell is formed of a MOS transistor having its gate g connected to a word line and having one of the source and drain regions s and d (for example, source s) grounded in a first metallization level of the structure. In FIG. 2B, the fact for a drain or source region d or s to be contacted by an upper metallization level has been illustrated by a point on the corresponding conductive line. As appears from this drawing, all the sources s of the transistors are shared by two transistors (and thus two memory cells) and are grounded by conductive lines parallel to the word lines. The transistor gates are formed in a polysilicon layer. To simplify the representation of the drawings, this polysilicon level has been voluntarily confounded with the word lines while in practice, these lines are formed in an upper metallization level and are connected to the gate regions by vias. The perpendicular bit and word lines are formed in two metallization levels above the cells.
The programming of each cell is performed by connecting or not the drain d of the involved transistor to the bit line of the corresponding cell. In the case where the drain is connected to the bit line, the memory cell is programmed to a low state. In the opposite case, it is programmed to a high state.
The reading of the memory cells of such an array is performed as follows. The bit line which must be read is precharged to a positive voltage level with respect to ground. Then, the memory cell to be read is addressed by means of the corresponding word line which turns on the cell transistor by application of a voltage on its gate. In the case where the bit line is connected to the transistor drain, the bit line discharges through the source of its grounded transistor and a low state is read by the amplifiers (3, FIG. 1). In the opposite case, the bit line is not discharged and provides a high state.
In FIG. 2B, it has been arbitrarily considered that the transistors of coordinates WLj-BLi+1, WLj+1-BLi, and WLj+1-BLi+1 were programmed to state zero (their drains are connected to the bit lines) while the other transistors are programmed to state one.
Other conventional example of a memory architecture are described in documents U.S. Pat. No. 6,556,468 and U.S. Pat. No. 6,363,001.
A problem of ROM cell arrays is linked to electromigration on the ground lines due to the significant number of cells likely to discharge the precharge current. When several parallel bit lines are precharged to the high level, the addressing of a word line to select the transistors of the corresponding intersections results in a discharge from the high state between the drain and the source of all the programmed transistors, to provide a zero value. The corresponding sum of the bit lines currents is then conveyed by the grounded conductive line. The intensity of the current to be conveyed by these grounded lines results either in oversizing said lines, and thus increasing the bulk, or in limiting the number of cells addressable in parallel in the memory plane, and thus the density.
Another disadvantage of ROM cells is due to the coupling between neighboring bit lines in the array. This phenomenon is due to the fact that, on precharge of the bit lines for reading the memory cells of a given word line, the discharge of a bit line having a grounded transistor of the addressed word line causes by coupling a decrease in the precharge voltage maintained on the neighboring line of a non-contacted transistor. This phenomenon is increased if the line on which a high state must be read is surrounded with two lines discharging to ground. This problem is more and more critical as memory cell arrays miniaturize and generates read errors.
A known solution to overcome this disadvantage is to differentially organize the reading of memory cells. Such a solution however requires be able to separately address two transistors of a same word line on two neighboring bit lines, which amounts to individualizing the word lines. This results in using two separate metallization levels to form the bit line conductors to be able to perform a plane-by-plane addressing. Such a solution has the disadvantage of decreasing the density of the structure. Further, it does not solve the problem of electromigration on ground conductors.
Another problem of known ROM architectures is due to the presence of shallow isolation trenches (STI) in the integrated structure to separate the transistors forming the cells.
FIG. 3 illustrates this problem in a very simplified cross-section view along a bit line of an N-channel MOS transistor structure on a P substrate, used for a ROM cell array. To simplify, the contact areas on the conductive lines have not been shown.
The transistors are formed in pairs (with a common source s) and the respective drains d of two transistors of a same pair are separated from the drains of the transistors of the neighboring pairs by means of STI shallow isolation trenches in both directions. This amounts to forming two transistors per well defined by means of isolation trenches. The size of such isolation trenches generates a physical stress on the transistors. Now, the greater this stress, the lower the current for given dimensions (gate width and length). This problem results in increasing the respective transistor sizes.